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INDEX
MX97102
ISDN S/T CONTROLLER
FEATURES
* Pin-to-Pin and Register-to-Register compatible with Siemens 2186 * Full duplex 2B+D ISDN S/T Transceiver according to CCITT I.430 * GCI digital interface * 3 types of 8-bit CPU interface * Receive timing recovery with adaptively switched thresholds * * * * * * * D-channel access control LAPD(HDLC) support with FIFO(2x64) buffers Activation/Deactivation Multiframing with S and Q bit access CPU access to B and IC channels Watchdog timer Package types : P-LCC-44, P-LQFP-64
GENERAL DESCRIPTIONS
MX97102 implements the 4-wire S/T interface used to link voice/data terminals to an ISDN. It is designed for the user site of the ISDN-basic access, two 64kbit/s B channels and a 16kbit/s D channel. MX97102 can be mainly divided into three portions according to their interfaces. Except these three interface functions, it also provides the LAPD controller which handles the HDLC packets of the ISDN D-channel for the associated microprocessor. The first, S/T interface controller, provides all electrical and logical functions of the S/T interface, such as S/T transceiver, activation/deactivation, timing recovery, multiframe S and Q channels, and D-channel access and priority control for communicating with remote equipments. The Second is the microprocessor interface controller which offers the registers compatible with Siemens PSB2186, provides three types of microprocessor interface, such as Motorola bus mode, Intel multiplexed mode and Intel non-multiplexed mode. The last portion is the GCI interface controller which is used to connect different voice/data application modules for local digital data exchangements.
PIN CONFIGURATION
44-PLCC
PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 PA1 PA2 PA0
64-PLQFP
PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 NC NC NC NC NC NC 35 NC 34 NC 33
48
47
46
45
44
43
42
41
40
39
38
37
PSDS1 PNC1 PRST PA5(EAW) VSSD PDCL PFSC1 PNC2 VSSD PNC3 PA4
7
6
1 44
40 39
NC
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
36
32 31 30 29 28 27 26 25
NC NC PA0 PRDN(D5) PWRN(R/W) PCSN PALE PIDP1 PIDP0 PSX2 PSX1 VDD NC NC NC NC
PRDN(DDS) PWRN(R/W) PCSN PALE PIDP1
PA2 PA1 PSDS1 PNC1 PRST PA5(EAW) NC VSSD PDCL PFSC1 PNC2 VSSD PNC3 PA4 PA3
12
MX97102
34
PIDP0 PSX2 PSX1 VDD PNC1
MX97102
24 23 22 21 20 19 18 17
17 18
PA3 PNC4 PNC5 VSSD PBCL
23
VSSA PXTAL2 PXTAL1 PSR2 PINTN
29 28
PSR1
PUFI
10
11
12
13
14 PSR2
15 NC
PNC4
NC
NC
PNC5
NC
VSSD
PBCL
PINTN
NC
VSSA
PXTAL2
PXTAL1
NC
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PSR1
16
1
2
3
4
5
6
7
8
9
INDEX
MX97102
BLOCK DIAGRAM
Control and Data Interface signals PIDP0 PIDP1 S/T Interface LAP-D
Transmitter Multiframe Activation/ control Deactivation Receiver DPLL 7.68MHZ OSC PDCL PFSC1
GCI Interface
B-channel Switching
FIFO WATCH DOG RESET SOURCE
uP Interface
PINTN microprocessor interface PRST
FIGURE 2: FUCTIONAL BLOCK DIAGRAM
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MX97102
PIN DESCRIPTION (44-PIN)
TABLE 1: MX97102 PIN DESCRIPTIONS PAD# 41 42 43 44 1 2 3 4 37 38 PIN NAME PAD0(D0) PAD1(D1) PAD2(D2) PAD3(D3) PAD4(D4) PAD5(D5) PAD6(D6) PAD7(D7) PCSN PWRN(R/W) I/O DESCRIPTION Multiplexed Bus Mode:Address/data bus from the CPU system to this device and data between the CPU system and this device, Non-Multiplexed Bus Mode:Data bus between the CPU system and this device.
I/O
I
I
39
PRDN(DS)
I
23 8, 4 16, 19 20,30 36
PINTN PNC1~PNC5 PUFI PALE
Open Drain
ChipSelect:A logic "LOW" enable this device for a read/write operation. Read/Write:A logic "HIGH" indicates a valid read operation by CPU. A logic "LOW" indicates a valid write operation by CPU.(Motorola bus mode) Write:A logic "LOW" indicates a write operation.(Intel bus mode) Data Strobe: The rising edge marks the end of a valid read or write operation (Motorola bus mode). Read:A logic "LOW" indicates a read operation.(Intel bus mode) Interrupt Request:The signal is a logic "LOW" when this device requests an interrupt. It is an open drain output. No used.
I
9
PRST
I/O
13 12
PFSC1 PDCL
O(I) O(I)
Address Latch Enable:A logic "HIGH" indicates an address on the address/ data bus(Multiplexed bus type only). ALE also selects the micro-processor interface type (multiplexed or non-multiplexed). Reset:A logic "HIGH" on this input forces this device into reset state. The minimum pulse length is four DCL-clock periods or four ms. If the terminal specific functions are enabled,this device may also output a reset signal. Frame Sync 1:Frame sync output. Logic "HIGH" during channel 0 on the GCI interface. This pin becomes Input if Test Mode is programmed (register ADF1). Data Clock:Clock of frequency, 1536kHz output, equals to twice the GCI data rate. This pin becomes Input if Test Mode is programmed (register ADF1)
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MX97102
TABLE 1: MX97102 PIN DESCRIPTIONS(Continued) PAD# 40 6 5 18 17 10 PIN NAME PA0 PA1 PA2 PA3 PA4 PA5(EAW) I/O DESCRIPTION (non-multiplexed bus mode) Address Bit 0 Address Bit 1 Address Bit 2 Address Bit 3 Address Bit 4 Address Bit 5; External Awake, when terminal specific function enabled, this pin is used as an external awake line. If a falling edge on this input is detected, it generates an interrupt and a reset pulse. Bit Clock:Clock of frequency 768kHz equal to the GCI data rate. Serial Data Strobe 1:A programmable strobe signal, selecting either one or two B or IC channels on GCI interface, is supplied via this line. (register ADF2) Digital ground Analog ground Power supply (5V5%) Connection for crystal or external clock input. Connection for external crystal. Left unconnected if external clock is used. S-Bus Receiver Input S-Bus Transmitter Output(positive) S-Bus Transmitter Output(negative) GCI-Data Port 0 (DD) GCI-Data Port 1 (DU) Open drain without internal pull-up resister or push-pull.
22 7
PBCL PSDS1
O O
11, 15 21 24 31 26 25 27 28 32 33 34 35
VSSD VSSA VDD PXTAL1 PXTAL2 PSR2 PSR1 PSX1 PSX2 PIDP0(DD) PIDP1(DU)
I O I O I/O
ABSOLUTE MAXIMUM RATINGS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
RATING Maximum Supply Voltage (VDD) DC Input Voltage on any pin Storage Temperature Range VALUE 6V -0.4Vto VDD+0.4V -55 to 150 C C
Operating Free Air Temperature Range 0 to 70 C C
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MX97102
DC CHARACTERISTICS
TABLE 3: DC CHARACTERISTICS Temperature from 0 to 70C; VDD = 5V5%, VSSA = 0V, VSSD = 0V Symbol Parameter Conditions Min. Value VIL L-input voltage -0.4 VIH H-input voltage 2.0 VOL L-output voltage IOL= 2mA VOL1 L-output voltage (IDP0) IOL= 7mA VOH H-output voltage IOH= -400uA 2.4 VOH H-output voltage IOH= -100uA VDD-0.5 ILI Input leakage current 0Max. Value 0.8 VDD+0.4 0.45 0.45
Unit V V V V V V
Remarks All pins except PSX1, PSX2, PSR1, PSR2
10 10 uA
All pins except BCL, PSX1,2, PSR1,2, PA0, PA1, PA3, PA4 PA0, PA1, PA3, PA4, BCL PSX1, PSX2
0120 2.31 2.39
uA
VX
V
IX RX
VSR1 VTR
RL = 5.6W Inactive or during binary one during binary zero RL = 50W Receiver output voltage IO < 5uA Receiver threshold Dependent on voltage (VSR2 - VSR1) peak level
7.5 10 0 2.35 225
13.4 kW W 2.6 375
mA
V mV
PSR1, PSR2
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MX97102
AC CHARACTERICS
TABLE 4: CRYSTAL SPECIFICATION PARAMETER Frequency Frequency calibration tolerance Load capacitance Oscillator mode SYMBOL f CL Limit values 7.680 max. 100 max. 50 fundamental UNIT MHz ppm pF
XTAL1 Clock Characteristics (external oscillator input) TABLE 5: CLOCK CHARACTERISTICS Parameter Limit values min. max. Duty cycle 1:2 2:1 Temperature from 0 to 70C, VDD = 5V5% Inputs are driven to 2.4V for a logical "1" and to 0.4V for a logical "0" . Timing measurements are made at 2.0V for a logical "1" and 0.8V for a logical "0". The AC-testing output is loaded with a 150pF capacitor.
TIMING WAVE FORM
MICROPROCESSOR INTERFACE TIMING----INTERL BUS MODE
tRR RD x CS
tRI
tDF tRD AD0-AD7 Data
FIGURE 3(a) MICROPRCESSOR READ CYCLE IN INTEL BUS MODE
tAA tAD
ALE WR x CS or RD x CS tAL AD0-AD7 Address tLA
tALS
FIGURE 3(b) MICROPROCESSOR WRITE CYCLE IN INTEL BUS MODE
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MX97102
tAA
tAD
ALE WR x CS or RD x CS tAL AD0-AD7 Address tLA
tALS
FIGURE 3(c) MULTIPLEXED ADDRESS TIMING IN INTEL BUS MODE
WR x CS or RD x CS tAS tAH Address
A0-A5
FIGURE 3(d) NON-MULTIPLEXED ADDRESS TIMING IN INTEL BUS MODE
MOTOROLA BUS MODE
ALE
tDSD tRWD
CS x DS
tRR tDF tRD
tRI
D0-D7
Data
FIGURE 4(a) MICROPROCESSOR READ TIMING IN MOTOROLA BUS MODE
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MX97102
R/W tDSD
CS x DS
tWW tWD tDW
tWI
D0-D7
Data
FIGURE 4(b) MICROPROCESSOR WRITE TIMING IN MOTOROLA BUS MODE
CS x DS tAS tAH Address
AD0-AD5
FIGURE 4(c) NON-MULTIPLEXED ADDRESS TIMING IN MOTOROLA BUS MODE
TABLE 6: PARAMETERS FOR MICROPROCESSOR INTERFACE TIMING PARAMETER ALE pulse witdh Address setup time to ALE Address hold time to ALE Address latch setup time to WR, RD Address setup time Address hold time ALE guard time DS delay after RW setup RD pulse width Data ouput delay from RD Data float from RD RD control interval W pulse width Data setup time to W, CS Data hold time from W, CS W control interval
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SYMBOL tAA tAL tLA tALS tAS tAH tAD tDSD tRR tRD tDF tRI tWW tDW tWD tWI
Limit Value min. 50 15 10 0 25 10 15 0 110
UNIT max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
110 25 70 60 35 10 70
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MX97102
APPLICATIONS
ISDN ACCESS ARCHITECTURE MX97102 is designed especially for subscriber terminal equipment with S/T interfaces, Four wire, two pairs for transmission and receiption separately, are connected to the NT equipment at the user site. Via the NT equipment, subscribers could dial up to the wide-area network with the traditional telephone line. The NT serves a converter between the U interface at the exchange and the S interface at the user premises. The NT may be either an NT1 only or an NT1 together with an NT2 connected via the T interface which is physically identical to the S interface. NT2 may include higher level functions like multiplexing and switching as in a PBX. Figure 5 illustrates the connections between the user site to the public domain of central office.
TE(1) S TE(8) S TE(1) LT-S LT-S LT-T T NT1 telephone line U
ISDN central office
LT
TE(1) S TE(8)
LT-S
PBX(NT2) NT1 LT
Direct Subscriber Access = MX97102 where - TE is an ISDN terminal - LT-S is a subscriber line termination - LT-T is a trunk line termination - LT is a trunk line termination in the central office
FIGURE 5 : ISDN - BASIC SUBSCRIBER ACCESS ACHITECTURE
MX97102 is based on the ISDN basic access, 192kbit/ s, which consists of two circuit-switched 64 kbit/s B channels and a message oriented 16kbit/s D channel for packetized data, signaling and telemetry information. The D channel is processed by the LAPD controller con-
tained in the MX97102 and routed via a parallel CPU interface to the terminal processor. The high level support of the LAPD protocol which is implemented by the MX97102 allows the use of a low cost processor in cost sensitive applications.
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MX97102
GCI CONNECTION With the GCI interface, MX97102 could connect different voice/data (V/D) application modules. Up to eight D-channel components may be connected to the D and C/I (Command/Indication) channels (TIC-bus). TIC-bus arbitration is also implemented in MX97102. Data transfers between the MX97102 and the V/D modules are done with the help of the GCI MONITOR channel protocol. Each V/D module can be accessed by an individual address. Two intercommunication channels IC1 and IC2 allow a 2*64kbit/s transfer rate between voice/data modules. Figure 6 shows one GCI connection, data module A uses D-channel for data transfer, a voice processor is connected to a programmable digital processing codec filter via IC1 and a data encryption module to a data device via IC2. Meanwhile, B1 is used for voice communication, B2 for data communication.
D, C/I
B1
B1
MX97102
Data Module A
Speech Processing
DSP Codec Module
Data Encryption
Data Module B
Microprocessor
Data Module
Speech Modules
Data Modules
FIGURE 6: EXAMPLES OF GCI CONNECTION
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MX97102
MICROPROCESSOR INTERFACE CONNECTION Single-chip microcontroller, such as 8048, 8031 or 8051, can meet the need of MX97102. MX97102 is built in various microprocessor interface, it fits perfectly into almost any 8-bit microprocessor system environment. The microprocessor interface can be selected to be either of the Motorola type (with control signals CS, R/W, DS) of the Siemens/Intel non-multiplexed bus type (with control signals CS, WR, RD) or of the Siemens/Intel multiplexed address/data bus type (with WR, RD, ALE).
+5V INT(INTX) RD WR ALE (PSCX) AD7....AD0 A15....A8 Latch PINTN PRDN PWRN PALE PCSN PAD7....0 MX97102 S PSX1 PSX2 PSR1 PSR2
80C51 (80C188)
Common Bus A15-A0, D7-D0
GCI
Memory
FIGURE 7: CONNECTING THE MX97102 TO INTEL MICROCONTROLLER
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MX97102
S/T INTERFACE Line transceiver functions for the S/T interface follows the electrical specifications of CCITTI.430. According to this standard, pseudo-ternary encoding with 100% pulse width is used on the S/T interface. For both receive and transmit direction, a 2:1 transformer is used to connect the MX97102 transceiver to the 4 wire S/T interface.
+5V * VDD 10uf PSX2 MX97102 VSSD VSSA PSR1 * PSR2 Receive Pair * 2:1 PSX1 * Transmit Pair 2:1
GND
Note : * ----- See MXIC design spec. document 8012-0530
FIGURE 8: MX97102 EXTERNAL S-INTERFACE CIRCUITRY
The receiver is changed as a threshold detector with adaptively switched threshold levels. Pin PSR1 delivers 2.5V as an output, which is the virtual ground of the input signal on pin PSR2.
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MX97102
INTERNAL REGISTER
TABLE 7: HDLC OPERATION AND STATUS REGISTERS
Addr. (hex) 00-1F FIFO 20 20 21 21 22 23 24 24 25 25 26 26 27 27 28 29 29 2A 2B 2B ISTA MASK STAR CMDR MODE TIMR EXIR XAD1 RBCL XAD2 SAPR SAP1 RSTA SAP2 TEI1 RHCR TEI2 RBCH STAR2 STAR2 R/W R W R W RME RME XDOV RMC RPF RPF XFW RRES MDS1 CNT XDU RSC RSC XRNR RNR MDS0 CNT PCE XPR XPR RRNR STI TMD V RFO TIN TIN MBR XTF RAC A SOV CISQ CISQ MAC1 XIF DIM2 L MOS SIN SIN X XME DIM1 U SAW EXI EXI MAC0 XRES DIM0 E WOV Tx/Rx FIFO address Interrupt Status Register Mask Register Status Register Command Register Mode Register Timer Register Extended Interrupt Register W R W R W R W W R W R R W TEI2 XAC 0 0 TEI2 VN1 0 0 TEI2 VN0 0 0 TEI2 OV 0 0 TEI2 RBC11 WFA 0 TEI2 RBC10 MULT MULT TEI2 RBC9 TREC 0 EA RBC8 SDET 0 SAPI1 SAPI1 SAPI1 RDA TEI1 RDO TEI1 CRC TEI1 SAPI2 SAPI2 SAPI2 SAPI1 RAB SAPI2 TEI1 SAPI1 SA1 SAPI2 TEI1 SAPI1 SA0 SAPI2 TEI1 CRI C/R MCS TEI1 0 TA 0 EA RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBC0 Transmit Address 1 Receive Frame Byte Count Low Transmit Address 2 Received SAPI Individual SAPI 1 Receive Status Register Individual SAPI 2 Individual TEI 1 Receive HDLC Control Individual TEI 2 Receive Fram Byte Count High Status Register 2 Status Register 2 Name R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description
R/W MDS2 R/W CNT R XMR
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MX97102
TABLE 8: SPECIAL PURPOSE REGISTERS
Addr. (hex) 30 31 31 32 32 33 33 34 34 35 36 37 37 38 38 39 3A 3A 3B 3B 3C SPCR CIR0 CIX0 MOR0 MOX0 CIR1 CIX1 MOR1 MOX1 C1R C2R B1CR STCR B2CR ADF1 ADF2 MOSR MOCR SQRR SQXR ADF3 R/W SPU R W R W R W R W R/W R/W R W R W R W R W WTC1 WTC2 TEM 0 0 MDA1 CI1E CI1E 0 MDR1 MER1 MRE1 IDC IDC CFS CFS 0 PFS 0 MAB1 MXC1 SYN SQIE 0 IOF ODS MDR0 MRE0 SQR1 SQX1 STM1 0 D1C2 MER0 MRC0 SQR2 SQX2 STM0 0 D1C1 MDA0 MXE0 SQR3 SQX3 MAX1 ITF D1C0 MAB0 MXC0 SQR4 SQX4 MAX0 R/W IMS TSF TBA2 TBA1 TBA0 ST1 ST0 SC1 SC0 CODR1 CODR1 CODR1 CODR1 CODR1 CODR1 MR1 CODX1 CODX1 CODX1 CODX1 CODX1 CODX1 1 MX1 1 SQC RSS 0 BAS BAC 0 TLP C1C1 C1C0 C2C1 C2C0 CIC1 1 Serial Port Control Reg. Command/Indication Receive 0 CODX0 CODX0 CODX0 CODX0 1 Command/Indication Transmit 0 MONITOR Receive 0 MONITOR Transmit 0 Command/Indication Receive 1 Command/Indication Transmit 1 MONITOR Receive 1 MONITOR Transmit 1 Channel Register 1 Channel Register 2 B1-Channel Register Sync Transfer Control Register B2-Channel Register Additional Feature Reg.1 Additional Feature Reg.2 MONITOR Status Reg. MONITOR Control Reg. S-,Q-Channel Receive Register S-,Q-Channel Transmit Register R/W 0 Additional Feature Reg.3 CODR0 CODR0 CODR0 CODR0 CIC0 Name R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description
MRC1 MXE1
ORDERING INFORMATION
PART NO. MX97102QC MX97102UC PACKAGE 44 PIN PLCC 64 PIN LQFP
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MX97102
REVISION HISTORY
Rev. No. 1.1 1.2 Description Preliminary release Change editing Add ordering information and revision history Change words in drawings Add "not used" pins in pin descriptions Page6, Table 3 changed Wording errors Change feature description Storage Temperature Range " -65 to 125C" replaced by "-55 to 150 C C C" Add 64-pin package Made for CD-ROM release Modify 64-pin package outline data 64 PIN P-LQFP PACKAGE INFORMATION content changed Page Date JULY/28/1997 NOV/1997
1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
P4
P16
NOV/1997 APR/14/1998 MAY/21/1998 JUN./15/1998 AUG/21/1998 SEP/15/1998 OCT/20/1998 OCT/27/1998
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INDEX
MX97102
PACKAGE INFORMATION
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
ITEM A B C D E F G H I J K L M N
NOTE:
MILLIMETERS 17.53 .12 16.59 .12 16.59 .12 17.53 .12 1.95 4.70 max. 2.55 .25 .51 min. 1.27 [Typ.] .71 .10 .46 .10 15.50 .51 .53 R .25 [Typ.]
INCHES .699 .005 .653 .12 .653 .12 .690 .12 .077 .185 max. .100 .010 .020 min. .050 [Typ.] .028 .004 .018.004 .610 .020 .025 R .010 [Typ.]
FG H I K 17 18 13 7 6
A B 1 44 40 39
33
CD
29 23 28 E N M J L
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
64-PIN PLASTIC LOW-PROFILE QUAD FLAT PACKAGE (P-LQFP)
A
ITEM A B C D E F G H I J K L M N O
NOTE:
MILLIMETERS 16 14 14 16 12 [Typ.] 1 [Typ.] 1 [Typ.] .35 .05 0.8 1 .6 .15 .15 .05 1.45 .05 .1 .05 1.6 [max.]
INCHES .63 .55 .55 .63 .47 [Typ.] .039 [Typ.] .039 [Typ.] .014 .002 .031 .039 .024.006 .006 .002 .057 .002 .004 .002 .063 [max.]
M F
B
C
D
E
O
N G I H J
L K
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
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INDEX
MX97102
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888 FAX:+886-3-578-8887
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TEL:+32-2-456-8020 FAX:+32-2-456-8021
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CHICAGO OFFICE:
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
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